Microchip Technology /ATSAME51J19A /DMAC /CHANNEL[20] /CHCTRLA

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CHCTRLA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SWRST)SWRST 0 (ENABLE)ENABLE 0 (RUNSTDBY)RUNSTDBY 0 (DISABLE)TRIGSRC0 (BLOCK)TRIGACT 0 (SINGLE)BURSTLEN 0 (1BEAT)THRESHOLD

TRIGSRC=DISABLE, THRESHOLD=1BEAT, BURSTLEN=SINGLE, TRIGACT=BLOCK

Description

Channel n Control A

Fields

SWRST

Channel Software Reset

ENABLE

Channel Enable

RUNSTDBY

Channel Run in Standby

TRIGSRC

Trigger Source

0 (DISABLE): Only software/event triggers

TRIGACT

Trigger Action

0 (BLOCK): One trigger required for each block transfer

2 (BURST): One trigger required for each burst transfer

3 (TRANSACTION): One trigger required for each transaction

BURSTLEN

Burst Length

0 (SINGLE): Single-beat burst length

1 (2BEAT): 2-beats burst length

2 (3BEAT): 3-beats burst length

3 (4BEAT): 4-beats burst length

4 (5BEAT): 5-beats burst length

5 (6BEAT): 6-beats burst length

6 (7BEAT): 7-beats burst length

7 (8BEAT): 8-beats burst length

8 (9BEAT): 9-beats burst length

9 (10BEAT): 10-beats burst length

10 (11BEAT): 11-beats burst length

11 (12BEAT): 12-beats burst length

12 (13BEAT): 13-beats burst length

13 (14BEAT): 14-beats burst length

14 (15BEAT): 15-beats burst length

15 (16BEAT): 16-beats burst length

THRESHOLD

FIFO Threshold

0 (1BEAT): Destination write starts after each beat source address read

1 (2BEATS): Destination write starts after 2-beats source address read

2 (4BEATS): Destination write starts after 4-beats source address read

3 (8BEATS): Destination write starts after 8-beats source address read

Links

()